1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for use in an in-plane switching mode liquid crystal display device (IPS-LCD).
2. Description of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite alignment direction as a result of their long, thin shapes. That alignment direction can be controlled by an applied electric field. In other words, as the direction of an applied electric field changes, so does the alignment of the liquid crystal molecules. Due to the optical anisotropy, the refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling an applied electric field, a desired light image can be produced.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
LCD devices have wide application in office automation (OA) equipment and video units because they are light and thin and have low power consumption characteristics. The typical liquid crystal display (LCD) panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs) and pixel electrodes.
As previously described, LCD device operation is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an electric field applied between the common electrode and the pixel electrode. Thus, the alignment direction of the liquid crystal molecules is controlled by the application of an electric field to the liquid crystal layer. When the alignment direction of the liquid crystal molecules is properly adjusted, incident light is refracted along the alignment direction to display image data. The liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
In a conventional LCD device, since the pixel and common electrodes are positioned on the lower and upper substrates, respectively, the electric field induced between them is perpendicular to the lower and upper substrates. However, the conventional LCD devices having the longitudinal electric field have a drawback in that they have a very narrow viewing angle. In order to solve the problem of narrow viewing angle, in-plane switching liquid crystal display (IPS-LCD) devices have been proposed. The IPS-LCD devices typically include a lower substrate where a pixel electrode and a common electrode are disposed, an upper substrate having no electrode, and a liquid crystal interposed between the upper and lower substrates. A detailed explanation about the lower substrate (i.e., array substrate) of the IPS-LCD device will be provided referring to figures.
FIG. 1 is a plan view illustrating one pixel of an array substrate of an in-plane switching mode liquid crystal display (IPS-LCD) device according to a related art. As shown, gate lines 12 are transversely disposed on a substrate (see reference element 10 of FIG. 2A). A common line 16 is spaced apart from the gate lines 12, and disposed adjacent to and parallel with the gate lines 12. Data lines 24 that are spaced apart from each other are disposed across and substantially perpendicular to the gate and common lines 12 and 16. A pair of data lines 24 and a pair of gate and common lines 12 and 16 define a pixel area P.
A switching device, e.g., a thin film transistor T, is positioned near the crossing of the gate and data lines 12 and 24. As shown in FIG. 1, the thin film transistor T includes a gate electrode 14, an active layer 20, a source electrode 26 and a drain electrode 28. The gate and source electrodes 14 and 26 are positioned and electrically connected with the gate and data lines 12 and 24, respectively. Namely, the gate electrode 14 extends from the gate line 12, while the source electrode 26 extends from the data line 24. The drain electrode 28 is spaced apart from the source electrode 26 and overlaps a portion of the active layer 20. The active layer 20 is located right above the gate electrode 14 and under the source and drain electrodes 26 and 28. Thus, the source electrode 26 and the drain electrode 28 overlap portions of the active layer 20, respectively.
In the pixel area P, a pixel electrode 30 connected to the drain electrode 28 is disposed. The pixel electrode 30 includes a horizontal portion 30a above the common line 16 and a vertical portion 30b parallel with the data lines 24. The horizontal and vertical portions 30a and 30b and the drain electrode 28 are formed as one united body. A common electrode 17 including first and second common electrodes 17a and 17b is also disposed in the pixel area P. The first and second common electrodes 17a and 17b extend from the common line 16 and are formed as one united body with the common line 16. The first and second common electrodes 17a and 17b are parallel with and adjacent to the data lines 24, respectively. Between the first and second common electrodes 17a and 17b, the vertical portion 30b of the pixel electrode 30 is positioned.
There is a storage capacitor C that is parallel-connected to the pixel at the top of the pixel area P. The storage capacitor C is formed of a portion of the common line 16, a horizontal portion 30a of the pixel electrode 30, and a dielectric layer (not shown). Namely, the portion of the common line 16 acts as a first electrode and the horizontal portion 30a of the pixel electrode 30 acts as a second electrode in the storage capacitor C. The common line 16 in the related art shown in FIG. 1 has a width W. When designing the common line 16 to have the width W, the width W of the related art should be as large as necessary so that the signal can easily flow through the common line 16 and the storage capacitor C can have an enough capacitance.
FIGS. 2A to 2C are cross sectional views taken along lines II—II and III—III of FIG. 1 and illustrate fabricating processes for the array substrate.
Referring to FIG. 2A, a first metal layer is formed on a substrate 10 and then patterned to form the gate line 12 (see FIG. 1), the gate electrode 14, the common line 16, and the first and second common electrodes 17a and 17b. Aluminum (Al), aluminum alloy (e.g., aluminum neodymium (AlNd)), chromium (Cr), molybdenum (Mo) or tungsten (W) is used as a material for the first metal layer. The gate electrode 14 protrudes from the gate line 12 (see FIG. 1). The common line 16 is adjacent to and parallel with the gate line. Further, the common line 16 is spaced apart from the gate line by a predetermined distance. As mentioned before, the first and second common electrodes 17a and 17b extend from the common line 16 and are disposed parallel with and adjacent to the data lines that are formed in a later step. Thereafter, a gate insulation layer 18 is formed on entire surface of the substrate 10 to cover the patterned first metal layer. Thus, for example, as shown in FIG. 2A, the gate electrode 14, the second common electrode 17b and the common line 16 are covered by the gate insulation layer 18. The gate insulation layer 18 is an inorganic material, such as silicon nitride (SiNx).
In FIG. 2B, an amorphous silicon layer (a-Si:H) and an impurity-included amorphous silicon layer (n+ a-Si:H) are sequentially formed on the gate insulation layer 18 and then patterned to form the active layer 20 and an ohmic contact layer 22. Particularly, the active layer 20 and the ohmic contact layer 22 are formed right above the gate electrode 14. Since the amorphous silicon layer (a-Si:H) and the impurity-included amorphous silicon layer (n+ a-Si:H) are simultaneously patterned, the active layer 20 is interposed between the ohmic contact layer 22 and the gate insulation layer 18.
Now in FIG. 2C, a second metal layer is formed on entire surface of the gate insulation layer 18 and then patterned to form the data lines 24, the source electrode 26, the drain electrode 28 and the pixel electrode 30 (including the horizontal portion 30a and the vertical portion 30b). As with the first metal layer, the second metal layer is one of chromium (Cr), aluminum (Al), aluminum alloy (e.g., AlNd), molybdenum (Mo), and the like. As shown and mentioned with reference FIG. 1, the data lines 24 cross both the gate line 12 and the common line 16, and define the pixel area P with both the gate line 12 and the common line 16. The source electrode 26 extends from the data line 24 and overlaps a portion of the ohmic contact layer 20. The horizontal portion 30a of the pixel electrode 30 is formed above the common line 16 to overlap a portion of the common line 16. The vertical portion 30b of the pixel electrode 30 extends from the horizontal portion 30a to the pixel area P and is disposed between the first and second common electrodes 17a and 17b parallel with the data lines. At the end of the vertical portion 30b of the pixel electrode 30, the drain electrode 28 is formed to overlap a portion of the ohmic contact layer 22. Since the source and drain electrodes 26 and 28 are spaced apart from each other, a portion of the ohmic contact layer 22 is removed using the source and drain electrodes 26 and 28 as a mask. Thus, a channel region is formed in the active layer 20 between the source and drain electrodes 26 and 28. The portion of the common line 16 and the horizontal portion 30a form the storage capacitor C. As mentioned before, the portion of the common line 16 acts as a first electrode of the storage capacitor, the horizontal portion 30a of the pixel electrode 30 acts as a second electrode of the storage capacitor, and the gate insulation layer 18 between the common line 16 and the horizontal portion 30a acts as a dielectric layer.
According to aforementioned structure of the array substrate shown in FIGS. 1 and 2A–2C, the array substrate for the IPS-LCD device has only one storage capacitor in the pixel. Thus, the common line acting as a first storage electrode needs to be designed to have large width for sufficient and satisfactory capacitance. In this case, since the common line is formed of an opaque material, the aperture ratio of the pixel becomes decreased.